1. Field of the Invention
The present invention relates generally to a semiconductor device, such as an electrically rewritable nonvolatile semiconductor memory device (EEPROM flash memory). More specifically, the invention relates to a flash memory system capable of simultaneously executing a data write or erase operation and a data read operation.
2. Description of the Related Background Art
Conventionally, there are various electronic systems wherein a plurality of memory devices are incorporated. For example, there is an electronic system wherein an EEPROM flash memory and an SRAM are incorporated to store data of the flash memory in the SRAM to exchange data between a CPU and the flash memory via the SRAM and to be capable of directly rewriting data of the flash memory without passing through the SRAM.
On the other hand, there is recently known a memory system called a read while write (RWW) type memory system capable of reading data out from a certain memory region while writing or erasing data in another memory region in order to reduce the number of memory chips necessary for the system. In order to form a memory device of this type, completely independent two memory regions may be simply provided in the memory device.
However, if the independently accessed regions are only simply provided in the memory device, there are problems as an RWW type memory system. First, since each of the memory regions independently requires a decoder and a sense amplifier, the layout area thereof is large. Secondly, if bit lines and word lines are continuously arranged independently every one of the memory regions, it is not possible to divide each of the memory regions into blocks to read and write data every block. That is, the range of the parallel execution of a data read operation and a data write operation is fixed, so that the system can not be applied to many uses. In order for the system to be applied many uses, a plurality of kinds of systems having different capacities of memory regions must be prepared.
In a conventional flash memory capable of simultaneously executing a data write or erase operation and a data read operation, a memory cell array is physically fixed to two banks. For example, considering a 32-Mbit flash memory chip, the capacity thereof is fixed so that one of the banks has 0.5 Mbits and the other bank has 31.5 Mbits. Therefore, users must newly buy another chip when requiring a different bank size.
In addition, as a circuit construction, dedicated address and data lines are provided every bank. When a write or erase operation is executed in blocks of one of banks, the power supply line of the one of the banks is connected to a writing or erasing power supply line by a power supply switch, and the power supply line of the other bank is connected to a reading power supply side. If the opposite operation instruction is inputted, each of the banks is connected to the power supply line on the opposite side by a corresponding one of the power supply switches.
Moreover, a set of sense amplifiers for detecting memory cell data are provided exclusively for each of the banks. For that reason, although it is possible to execute a read operation from memory cells in one of the banks while executing a write or erase in blocks in the other bank, it is impossible to simultaneously execute a write or erase operation and a read operation in the same bank.
In addition, since the banks are physically fixed, there is a severe limit to addresses capable of being simultaneously executed, and the size of each of the banks is also fixed, so that the degree of freedom is very low.